Multiple-output multilevel logic circuits synthesis technique using multiplexers

Abstract

In this paper a new efficient synthesis technique for multiple-output multilevel combinational logic circuits is described.  For an implementation of logic circuits the use of universal logic modules - multiplexers - is assumed.  The decomposition of collection m functions of n variables and the reduction  of canonical multiplexer trees are made by means of the table of residue functions.  The resulting circuits are well suited for FPGA's implementations.  The synthesis technique presented has been implemented in TURBO C++ on PC under MS-DOS. The computer program creates such a tree structure, which contains a minimum number of logic levels and multiplexers.