A Simple PLL-Based True Random Number Generator for Embedded Digital Systems


  • Miloš Drutarovský
  • Martin Šimka
  • Viktor Fischer
  • Frédéric Celle


Cryptography, FPGA, PLL, clock jitter, TRNG, DIEHARD, NIST, statistical tests


The paper presents a simple True Random Number Generator (TRNG) which can be embedded in digital Application Specific Integrated Circuits (ASICs) and Field Programmable Logic Devices (FPLDs). As a source of randomness, it uses on-chip noise generated in the internal analog Phase-Locked Loop (PLL) circuitry. In contrast to traditionally used free-running oscillators, it uses a novel method of randomness extraction based on two rationally related synthesized clock signals. The generator has been developed for embedded cryptographic applications, where it significantly increases the system security, but it can be used in a wide range of other applications. The functionality of the proposed solution is demonstrated for the Altera Apex FPLD family, but the same principle can be used for all recent ASICs or FPLDs that include an on-chip reconfigurable analog PLL. The quality of the TRNG output is confirmed by applying special DIEHARD and NIST statistical tests, which pass even for high output bit-rates of several hundreds of Kbits/s.


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How to Cite

Drutarovský, M., Šimka, M., Fischer, V., & Celle, F. (2012). A Simple PLL-Based True Random Number Generator for Embedded Digital Systems. COMPUTING AND INFORMATICS, 23(5-6), 501–515. Retrieved from https://www.cai.sk/ojs/index.php/cai/article/view/442