An Evolvable Combinational Unit for FPGAs
Keywords:Combinational circuit, evolutionary design, evolvable hardware, field programmable gate array
AbstractA complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evolutionary algorithm was described in VHDL independently of a target platform, i.e. as a soft IP core, and realized in the COMBO6 card. In many cases the unit is able to evolve (i.e. to design) the required function automatically and autonomously, in a few seconds, only on the basis of interactions with an environment. A number of circuits were successfully evolved directly in the FPGA, in particular, 3-bit multipliers, adders, multiplexers and parity encoders. The evolvable unit was also tested in a simulated dynamic environment and used to design various circuits specified by randomly generated truth tables.
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How to Cite
Sekanina, L., & Friedl, Štěpán. (2012). An Evolvable Combinational Unit for FPGAs. COMPUTING AND INFORMATICS, 23(5-6), 461–486. Retrieved from https://www.cai.sk/ojs/index.php/cai/article/view/440