A Flip-Flop Matching Engine to Verify Sequential Optimizations


  • Solaiman Rahim
  • Bruno Rouzeyre
  • Lionel Torres


Equivalence checking, synthesis, matching, combinational equivalence checking, sequential optimizations, redundancy removal, don´t care conditions


Equivalence checking tools often use a flip-flop matching step to avoid the state space traversal. Due to sequential optimizations performed during synthesis (merge, replication, redundancy removal, ...) and don't care conditions, the matching step can be very complex as well as incomplete. If the matching is incomplete, even the use of a fast and efficient SAT solver during the combinational equivalence-checking step may not prevent the failure of this approach. In this paper, we present a flip-flop matching engine, which is able to verify optimized circuits and handle don't care conditions.


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How to Cite

Rahim, S., Rouzeyre, B., & Torres, L. (2012). A Flip-Flop Matching Engine to Verify Sequential Optimizations. COMPUTING AND INFORMATICS, 23(5-6), 437–460. Retrieved from https://www.cai.sk/ojs/index.php/cai/article/view/439