Testability Analysis and Improvements of Register-Transfer Level Digital Circuits
Keywords:Digital circuit, testing, register-transfer level, data path, testability analysis, design for testability, scan technique
AbstractThe paper presents novel testability analysis method applicable to register-transfer level digital circuits. It is shown if each module stored in a design library is equipped both with information related to design and information related to testing, then more accurate testability results can be achieved. A mathematical model based on virtual port conception is utilized to describe the information and proposed testability analysis method. In order to be effective, the method is based on the idea of searching two special digraphs developed for the purpose. Experimental results gained by the method are presented and compared with results of existing methods.
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How to Cite
Strnadel, J. (2012). Testability Analysis and Improvements of Register-Transfer Level Digital Circuits. COMPUTING AND INFORMATICS, 25(5), 441–464. Retrieved from https://www.cai.sk/ojs/index.php/cai/article/view/353