BP-NUCA: Cache Pressure-Aware Migration for High-Performance Caching in CMPs

Authors

  • Xiaomin Jia
  • Jiang Jiang
  • Yongwen Wang
  • Shubo Qi
  • Tianlei Zhao
  • Guitao Fu
  • Minxuan Zhang

Keywords:

Chip multi-processors (CMPs), last-level cache (LLC), block migration, non-uniform cache architecture (NUCA)

Abstract

As the momentum behind Chip Multi-Processors (CMPs) continues to grow, Last Level Cache (LLC) management becomes a crucial issue to CMPs because off-chip accesses often involve a big latency. Private cache design is distinguished by smaller local access latency, good performance isolation and easy scalability, thus is becoming an attractive design alternative for LLC of CMPs. This paper proposes Balanced Private Non-Uniform Cache Architecture (BP-NUCA), a new LLC architecture that starts from private cache design for smaller local access latency and good performance isolation, then introduces a low cost mechanism to dynamically migrate private blocks among peer private caches of LLC to improve the overall space utilization. BP-NUCA achieves this by measuring the cache access pressure level that each cache set experiences at runtime and then using the information to guide block migration among different private caches of LLC. A heavily accessed set, namely a set with high access pressure level, is allowed to migrate its evicted blocks to peer private caches, replacing blocks of sets which are with the same index and have low access pressure level. By migrating blocks from heavily accessed cache sets to less accessed cache sets, BP-NUCA effectively balances space utilization of LLC among different cores. Experimental results using a full system CMP simulator show that BP-NUCA improves the overall throughput by as much as 20.3 %, 12.4 %, 14.5 % and 18.0 % (on average 7.7 %, 4.4 %, 4.0 % and 6.1 %) over private cache, shared cache, shared cache management scheme UCP and private cache organization CC respectively on a 4-core CMP for SPEC CPU2006 benchmarks.

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Author Biographies

Xiaomin Jia

Department of Microelectronics
School of Computer
National University of Defense Technology
Changsha 410073, China

Jiang Jiang

Department of Microelectronics
School of Computer
National University of Defense Technology
Changsha 410073, China

Yongwen Wang

Department of Microelectronics
School of Computer
National University of Defense Technology
Changsha 410073, China

Shubo Qi

Department of Microelectronics
School of Computer
National University of Defense Technology
Changsha 410073, China

Tianlei Zhao

Department of Microelectronics
School of Computer
National University of Defense Technology
Changsha 410073, China

Guitao Fu

Department of Microelectronics
School of Computer
National University of Defense Technology
Changsha 410073, China

Minxuan Zhang

Department of Microelectronics
School of Computer
National University of Defense Technology
Changsha 410073, China

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Published

2012-01-26

How to Cite

Jia, X., Jiang, J., Wang, Y., Qi, S., Zhao, T., Fu, G., & Zhang, M. (2012). BP-NUCA: Cache Pressure-Aware Migration for High-Performance Caching in CMPs. Computing and Informatics, 30(5), 1037–1060. Retrieved from https://www.cai.sk/ojs/index.php/cai/article/view/208