PAFSV: A Formal Framework for Specification and Analysis of SystemVerilog
Keywords:SystemVerilog, process algebras, formal semantics, PAFSV, formal specification and analysis, circuit verification
AbstractWe develop a process algebraic framework PAFSV for the formal specification and analysis of IEEE 1800TM SystemVerilog designs. The formal semantics of PAFSV is defined by means of deduction rules that associate a time transition system with a PAFSV process. A set of properties of PAFSV is presented for a notion of bisimilarity. PAFSV may be regarded as the formal language of a significant subset of IEEE 1800TM SystemVerilog. To show that PAFSV is useful for the formal specification and analysis of IEEE 1800TM SystemVerilog designs, we illustrate the use of PAFSV with a multiplexer, a synchronous reset D flip-flop and an arbiter.
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How to Cite
Man, K. L., Lei, C.-U., Kapoor, H. K., Krilavicius, T., Ma, J., & Zhang, N. (2016). PAFSV: A Formal Framework for Specification and Analysis of SystemVerilog. COMPUTING AND INFORMATICS, 35(1), 143–176. Retrieved from https://www.cai.sk/ojs/index.php/cai/article/view/1371