Pipeline Implementation of Peer Group Filtering in FPGA

Authors

  • Tomasz Kryjak AGH University of Science and Technology, al. Mickiewicza 30, 30-065 Cracow
  • Marek Gorgon AGH University of Science and Technology, al. Mickiewicza 30, 30-065 Cracow

Keywords:

Colour image processing, reconfigurable systems, FPGA, parallel algorithms

Abstract

In the paper a parallel FPGA implementation of the Peer Group Filtering algorithm is described. Implementation details, results, performance of the design and FPGA logic resources are discussed. The PGF algorithm customized for FPGA is compared with the original one and Vector Median Filtering.

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Published

2012-10-03

How to Cite

Kryjak, T., & Gorgon, M. (2012). Pipeline Implementation of Peer Group Filtering in FPGA. COMPUTING AND INFORMATICS, 31(4), 727–741. Retrieved from https://www.cai.sk/ojs/index.php/cai/article/view/1102

Issue

Vol. 31 No. 4 (2012): Computing and Informatics

Section

Articles