Call for Papers - Next Generation On-Chip Networks for Multicore Systems

Scope and purpose:

The popularity of multi-core and many-core systems are increasing day by day. With such a rise in demand, it becomes essential to innovate and explore the network on-chips field to facilitate communication among various modules of a multi-core or many-core system. Such system architectures need communication that is scalable and supports high bandwidth. Network on-chips are the right choice to help them achieve this. There has been a lot of research and developments in the next generation of on-chip networks for multicore systems. A lot of focus has been given to resolving some of the key issues such as efficiency, scalability, and reusability. One of the ways to improve the network bandwidth of on-chip networks is through multiple network-on-chip (multi-NoC) architecture. However, it comes at the cost of communication infrastructure performance. This can be overcome through wireless-assisted multiple network-on-chip applications whose free spectral range can be controlled by a novel system. This system generates a discrete set of frequencies that can be controlled by microring resonators.

Next-generation on-chip networks are focused on novel network topology designs that consist of smaller, efficient, and high-performance nodes that are embedded into a network fabric architecture. Such a distributed type of architecture will improve the resiliency, scalability, and operational efficiency of on-chip networks for multicore systems. Novel system architectures leverage elements that can be orchestrated with the help of automation to form an easily manageable multicore system. Such intelligent network systems can detect network congestion and other irregular events. Automatic action will be then triggered to reroute or alter the flow of traffic based on the predefined service level agreement parameters. The benefits of such innovative network architectures include the following: improved resiliency during outage events with the help of automatic alternate path routing, load shifting at peak usage times based on threshold controls for congestion management, segment routing for customised service levels, servicing or maintenance of nodes without disrupting the traffic, clod-based network testing environments etc. Another focus factors for next-generation on-chi networks for multicore systems include power efficiency. This is being achieved through a novel Dynamic Voltage Scaling (DVS) technique in which there are no performance overheads. A reconfigurable arbitration logic makes sure that multiple latencies for different slack times can be constructed. This special issue on “Next Generation On-Chip Networks for Multicore Systems” tends to provide a platform for researchers to provide their unique work against this domain.

Topics include, but are not limited to:

• Methods to avoid message-dependent deadlocks for high-level protocols in an on-chip network for multicore systems
• Design and development of high-performance and customised NoCs for specific applications
• Modelling of power and area for network-on chips using automation
• Novel techniques for fault tolerance in NoCs using cloud-based reconfigurable links
• Stochastic communication design for next-generation network-on chips
• Direct Sequence Spread Spectrum coding for designing next-generation NoC architecture
• Innovative architecture and system design for developing slack-time-aware routing in NoCs
• QoS architecture for high-performance and resilient network on-chips
• Methods to enable adaptive routing in network on-chips for multicore systems
• Evaluation of algorithms that enable routing on NoCs based on meshes

Tentative Dates:
Submission Deadline: July 25, 2023
Authors Notification: October 15, 2023
Revised Version Submission: January 15, 2023
Final Decision Notification: March 20, 2024

Guest Editors:
Dr. Chi Lin, Institute of Intelligent System, Dalian University of Technology, Dalian, China
Prof. Chang Wu Yu, Chung Hua University, Hsinchu, Taiwan
Dr. Ning Wang, Computer Science & Research, Rowan University, Glassboro, New Jersey, USA