A Hybrid Architecture for Multimedia Processors

Abstract

Novel algorithmic features of multimedia applications and System on Chip (SoC) design using state-of-the-art CMOS technology are driving forces behind new multimedia processors. In this paper we propose an architecture that - based on this approaching technology - provides high performance and flexibility. It is a hybrid design consisting of instruction systolic arrays (ISAs) to be used as a special-purpose accelerator and RISC cores to be used as the basis of a general-purpose processor. It is a hierarchical and scalable architecture, which facilitates the hardware-/software codesign of multimedia processing circuits and systems. While some control-intensive functions can be implemented using the general-purpose CPU, other computation-intensive functions can rely on the accelerator.