High-Level Technology Mapping for Memories

Authors

  • Haifeng Zhou
  • Zhenghui Lin
  • Wei Cao

Keywords:

Circuit CAD, digital circuit design, high-level synthesis, technology mapping

Abstract

In this paper, we consider memory-mapping problems in High-Level Synthesis. We focus on the port mapping, bit-width mapping and word mapping, respectively. A 0-1 Integer Linear Programming (ILP) technique is used to solve the mapping problems, which synthesizes the source memory using one or more memory modules from a target memory library at a higher level. This method can not only perform bit-width mapping and word mapping, but it can also perform port mapping at the same time. Experimental results indicate that ILP approach is an effective method for memory reuse in high-level synthesis.

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Published

2012-02-20

How to Cite

Zhou, H., Lin, Z., & Cao, W. (2012). High-Level Technology Mapping for Memories. COMPUTING AND INFORMATICS, 22(5), 427–438. Retrieved from https://www.cai.sk/ojs/index.php/cai/article/view/463