Parallel Tiled Code Generation with Loop Permutation within Tiles

Authors

  • Marek Palkowski West Pomeranian University of Technology
  • Wlodzimierz Bielecki West Pomeranian University of Technology

Keywords:

Optimizing compilers, tiling, loop permutation, transitive closure, dependence graph, code locality, automatic parallelization

Abstract

An approach of generation of tiled code with an arbitrary order of loops within tiles is presented. It is based on the transitive closure of the program dependence graph and derived via a combination of the Polyhedral and Iteration Space Slicing frameworks. The approach is explained by means of a working example. Details of an implementation of the approach in the TRACO compiler are outlined. Increasing tiled program performance due to loop permutation within tiles is illustrated on real-life programs from the NAS Parallel Benchmark suite. An analysis of speed-up and scalability of parallel tiled code with loop permutation is presented.

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Author Biographies

Marek Palkowski, West Pomeranian University of Technology

Marek Palkowski has graduated and obtained his PhD degree in Computer Science from the Technical University of Szczecin, Poland. The main goal of his research is extracting parallelism and tiling from program loops, and developing the TRACO compiler.

Wlodzimierz Bielecki, West Pomeranian University of Technology

Prof. Wlodzimierz Bielecki is head of the Software Technology Department of the West Pomeranian University of Technology, Szczecin. His research interest includes parallel and distributed computing, optimizing compilers, extracting both fine- and coarse grained parallelism available in program loops.

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Published

2018-02-09

How to Cite

Palkowski, M., & Bielecki, W. (2018). Parallel Tiled Code Generation with Loop Permutation within Tiles. COMPUTING AND INFORMATICS, 36(6), 1261–1282. Retrieved from http://www.cai.sk/ojs/index.php/cai/article/view/2017_6_1261